1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor device and, more particularly, to a method of forming a capacitor of semiconductor devices which is designed to increase the capacitor capacity by maximizing the area of the lower electrode of the capacitor.
2. Discussion of Related Art
With a development of semiconductor devices, many studies have been made to integrate more devices on a single semiconductor chip.
Especially, a variety of cell structures have been suggested in order to minimize the size of device in the dynamic random access memory (DRAM) cell.
It is desirable to construct the memory cell with one transistor and one capacitor in an aspect that the area of the device on a chip should be minimized for the sake of a very large integration.
In such a memory cell having one capacitor, signal charges are stored in the lower electrode (storage node) of a capacitor connected to the transistor (switching transistor).
With a decrease in the size of the memory cell owing to large integration of the semiconductor memory device, the capacitor becomes smaller and accordingly the number of the signal charges storable in the lower electrode decreases.
It is thus necessary that the lower electrode of the capacitor of the memory cell should be greater than a predetermined value in order to secure a capacitor capacity required to transfer desired signals without a malfunction.
To minimize the size of the memory cell, the lower electrode of capacitor must be large in area relatively within a limited region on a semiconductor substrate.
Various methods have been proposed as to enhance the surface area of the lower electrode of the capacitor.
Hereinafter, a method of forming a capacitor of semiconductor devices according to prior art will be described with reference to the accompanying drawings.
FIGS. 1a-1h are cross-sectional views for illustrating the method of forming a capacitor of semiconductor devices according to the prior art.
As shown in FIG. 1a, a first oxide layer 12 is formed on a semiconductor substrate 11 and a nitride layer 13 being formed on the first oxide layer 12.
A photoresist (not shown) is then deposited on the nitride layer 13. A photo-etching process is performed to selectively remove the nitride layer 13 and the first oxide layer 12 so as to expose a defined portion of the surface of the semiconductor substrate 11, forming a plurality of contact holes 14.
As shown in FIG. 1b, polysilicon is deposited on the entire surface of the semiconductor substrate 11 including the contact holes 14. The entire surface of the resulting material is subjected to etch back process or chemical mechanical polishing (CMP) process, forming a plug 15 inside each of the contact hole 14.
As shown in FIG. 1c, a second oxide layer 16 is formed on the entire surface of the semiconductor substrate 11 including the plugs 15.
After the subsequent deposition of photoresist 17 on the second oxide layer 16, the photoresist 17 is patterned by exposure and development.
As shown in FIG. 1d, the patterned photoresist 17 is used as a mask in selectively removing the second oxide layer 16 to expose the surface of the nitride layer 13 adjacent to the plugs 15.
The nitride layer 13 is used as an etching stopper layer in selectively removing the second oxide layer 16.
As shown in FIG. 1e, the photoresist 17 is removed and the second oxide layer 16 selectively removed is wet-etched to broaden a region in which the lower electrode of capacitor will be formed.
That means, the capacitor capacity of the lower electrode that will be formed later is enhanced because the distance between the lower electrodes of the capacitor decreases by selectively removing the second oxide layer 16 by the wet etching process.
In performing the wet etching, the second oxide layer 16 is etched further in the upper part than the lower part because of the loading effect.
Unexplained part "A" is a portion of the second oxide layer 16 removed by the wet etching.
As shown in FIG. 1f, a conductive layer 18 for the lower electrode of the capacitor electrically connected to each of the plug 15 is formed on the entire surface of the semiconductor substrate 11 including the remaining second oxide layer 16. A third oxide layer 19 is then formed on the conductive layer 18.
As shown in FIG. 1g, an etch back process or CMP process is performed on the entire surface of the second oxide layer 19 and the conductive layer 18 so as to expose the surface of the second oxide layer 16, selectively removing the third oxide layer 19 and the conductive layer 19 and forming a lower electrode 18a of capacitor having an inner-type crown structure.
As shown in FIG. 1h, a wet etching is performed to remove the third oxide layer 19 and the second oxide layer 16. On the lower electrode 18a of capacitor are sequentially formed dielectric layer 20 and upper electrode 21 of capacitor, finally completing the related art process for forming a capacitor.
In the related art method of forming a capacitor of semiconductor devices, however, there are several problems as folLows.
First, an additional wet etching process is required in reducing the distance between the lower electrodes in the photo-etching process when fabricating an inner-type capacitor. Thus the process becomes complicated.
That means, it is necessary to carry out another wet etching process because the minimum distance between the lower electrodes in the 256M DRAM is less than 0.1 .mu.m and thus defining a desired distance between the lower electrodes in the photo-etching process is difficult to realize.
Second, uniform wet etching of the entire cells is not easy to realize because the area to be wet-etched is increased with an inclination that the capacitor increases in height, and the aspect ratio becomes larger.
Third, the upper part of the lateral sides of each cell is further wet-etched due to the loading effect in such a manner that it is impossible to reduce the distance between the lower electrodes sufficiently.